1. Field of the Invention
The present disclosure relates to a display device having an oxide thin film transistor (TFT) and its fabrication method and, more particularly, to a display device having an oxide TFT capable of simplifying a fabrication process and reducing a fabrication cost by forming a source metal layer on a gate pad, and its fabrication method.
2. Discussion of the Related Art
Recently, the development of diverse portable electronic devices such as mobile phones, personal digital assistants (PDAs), notebook computers, etc., has lead to an increase in the demand for a high picture quality large display devices as well as a light, thin, short, and small display devices, and thus, flat panel display (FED) devices are commonly used. The FEDs include a liquid crystal display (LCD) or a plasma display device (PDP), and currently, the LCD receives much attention as it can be mass-produced, has a driving unit that can be easily driven, implement a high picture quality, and drives the driving unit at low power consumption.
The LCD includes a color filter substrate, an array substrate, and a liquid crystal layer formed between the color filter substrate and the array substrate.
An active matrix (AM) driving method commonly used for the LCD is a method in which liquid crystal molecules in a pixel part are driven by using amorphous silicon thin film transistors (a-Si TFTs) as switching elements.
The structure of the general LCD will now be described with reference to FIG. 1.
FIG. 1 is an exploded perspective view schematically showing the general LCD. As shown in FIG. 1, the LCD includes a color filter substrate 5, an array substrate 10, and a liquid crystal layer 30 formed between the color filter substrate 5 and the array substrate 10.
The color filter substrate 5 includes a color filter (C) including a plurality of sub-color filters 7 that implement red, green and blue colors, a black matrix 6 demarcating the sub-color filters 7 and blocking light transmission through the liquid crystal layer 30, and a transparent common electrode 8 for applying voltage to the liquid crystal layer 30.
The array substrate 10 includes gate lines 16 and data lines 17 which are arranged vertically and horizontally to define a plurality of pixel areas (P), TFTs (T), switching elements, formed at respective crossings of the gate lines 16 and the data lines 17, and pixel electrodes 18 formed at the pixel areas (P).
A gate pad 18 and a data pad 19 are formed at each of end portions of the gate lines 16 and the data lines 17. A gate driving circuit and a data driving circuit are connected with the gate pad 18 and the data pad 19 to apply a scan signal and an image signal through the gate lines 16 and the data lines 17.
The color filter substrate 5 and the array substrate 10 are attached in a facing manner by a sealant (not shown) formed at edges of an image display area of the color filter substrate 5 and the array substrate 10 to form a liquid crystal panel, and the attachment of the color filter substrates 5 and the array substrate 10 is made by an attachment key formed on the color filter substrate 5 or the array substrate 10.
The LCD largely uses amorphous silicon as a switching element. Because the amorphous silicon incurs a low fabrication cost and can be fabricated at a low temperature, it is commonly used as the switching element of the LCD.
However, amorphous silicon is a very small mobility and has bad electrostatic properties, so when it is used in fabricating a large high quality display device, its picture quality is degraded. Thus, as a solution to the problem, TFTs are fabricated with polycrystalline silicon, but the TFTs made of polycrystalline incurs a high fabrication cost, has difficulty in having uniform characteristics when a large scale display device is intended, and needs to perform its process at a high temperature. In addition, like the amorphous silicon, the polycrystalline silicon has poor electrostatic properties.
Thus, in an effort to solve the problem, recently, an oxide TFT using oxide semiconductor has been proposed. A fabrication process of the oxide TFT is performed at a low temperature and the oxide TFT has better electrostatic properties compared with the polycrystalline silicon. Thus, the oxide TFTs have an advantage in that when they are applied to an LCD, they can have uniform characteristics at a low cost.
FIG. 2 is a sectional view of the LCD of FIG. 1, showing the structure of the LCD having an oxide TFT as a switching element. In the drawing, a pixel area where an image is actually implemented and a pad area connected with an external driving circuit to apply a signal to the pixel area are shown to be divided for the sake of brevity.
As shown in FIG. 2, the LCD includes first and second substrates 20 and 40 which face each other, and a liquid crystal layer 30 formed between the first and second substrates 20 and 40.
The first substrate 20 is an array substrate, an oxide TFT (T) is formed on a pixel area of the array substrate. The TFT (T) includes a gate electrode 21 formed on the first substrate 20, a gate insulating layer 26 formed on the entire surface of the first substrate 20 to cover the gate electrode 21, an oxide semiconductor layer 22 formed on the gate insulating layer 26, and a source electrode 23 and a drain electrode 24 formed on the oxide semiconductor layer 22. A passivation layer 30 is formed on the entire surface of the first substrate 20 to cover the TFT (T).
On the first substrate 20 of the pad area, there are formed a gate pad 18 and a transparent conductive layer 29a formed on the gate pad 18 to prevent the gate pad 18 from being oxidized during a process. Although not shown, a data pad and a transparent conductive layer are formed on the gate insulating layer 26 of the pad area, to which an external signal is inputted.
A pixel electrode 29 is formed on the passivation layer 28. It is electrically connected with the drain electrode 24 of the TFT via a contact hole formed at the passivation layer 28 to apply an image signal through the oxide TFT (T).
The color filter layers 7 implementing an actual color are formed on a pixel area of the second substrate 20, and black matrixes 42 blocking light transmission to the non-display area of the pixel area and the pad area.
However, the related art LCD device having such oxide semiconductor layer has the following problems.
That is, in these LCD devices, the gate insulating layer 26 is made of a nitride inorganic insulating material such as SiNx, and the passivation layer 28 is made of an oxide organic insulating material such as SiO2. The reason for using SiNx as the material of the gate insulating layer 26 and SiO2 as the material of the passivation layer 28 is as follows. A channel layer where electrons flow actually in the oxide semiconductor layer 22 is formed along the upper surface of the oxide semiconductor layer 22. Thus, if SiNx, not SiO2, is used as a material of the passivation layer 28 in contact with the upper surface of the oxide semiconductor layer 22, oxygen is captured to the passivation layer 28 from the interface of the oxide semiconductor layer 22 and the passivation layer 28 to degrade crystallinity (i.e., crystalline properties) in the vicinity of the interface (namely, in the vicinity of the upper surface of the oxide semiconductor layer 22). The degradation of such crystallinity brings about degradation of electric conductivity of the corresponding area, so the characteristics of the oxide TFT deteriorate. For this reason, the gate insulating layer 26 of the oxide TFT is made of the nitride inorganic insulating material such as SiNx and the passivation layer 28 is made of an oxide organic insulating material such as SiO2.
In this case, the nitride inorganic insulating material is etched by a dry etching method, while the oxide organic insulating material is etched by a wet etching method. Thus, the difference in the etching method causes a problem in the process when the gate insulating layer 26 and the passivation layer 28 at the pad area. FIGS. 3a to 3e show the process of etching the gate insulating layer 26 and the passivation layer 28. Substantially, the gate insulating layer 26 and the passivation layer 28 are etched in the process of forming a contact hole for electrically connecting the drain electrode 23 and the pixel electrode 29 of the oxide TFT (T) after the oxide TFT (T) of the pixel area is formed, but, for the sake of brevity, only the etching of the gate insulating layer 26 and the passivation layer 28 at the pad area will be described with reference to the drawings.
With reference to FIG. 3a, a photoresist layer 54a is formed on the gate insulating layer 26 and the passivation layer 28 deposited on the first substrate 20 of the pad area, and developed by using a photo mask to form a photoresist pattern 54b as shown in FIG. 3b. Subsequently, an etching solution is applied with the passivation layer blocked with the photoresist pattern 54b to etch the passivation layer 28.
Then, when an etching gas is applied to the exposed gate insulating layer 26 as shown in FIG. 3c, the gate insulating layer 26 is etched to make the gate pad 18 exposed as shown in FIG. 3d. In this case, when the gate insulating layer 26 is etched by using the etching gas, the gate insulating layer 26 is isotropic-etched, generating an undercut at the gate insulating layer 26 below the passivation layer 28 as shown in FIG. 3d, so an overhang (A) is generated at the passivation layer 28.
The overhang (A) of the passivation layer 28 causes a transparent conductive layer 29a to be disconnected when the transparent conductive layer 29a is formed in a follow-up process, so as shown in FIG. 3d, the etching solution is applied to etch out the overhang (A) formed at the passivation layer 28.
Thereafter, as shown in FIG. 3e, a transparent conductive material is deposited on the overhang (A)-removed passivation layer 28 to form the transparent conductive layer 29a. 
As described above, in the related art LCD having the oxide TFT, in the gate pad 18 by etching the gate insulating layer 26 and the passivation layer 28 formed over the gate pad 18, the process of removing the overhang (A) formed at the passivation layer 28, as well as the etching process of the gate insulating layer 26 and the etching process of the passivation layer 28, is additionally performed.